(1) Field of the Invention
The present invention relates to a register control circuit, and more particularly to a register control circuit for initializing registers without a dedicated reset input.
(2) Description of the Related Art
Conventionally, an initialization of a D-type flip-flop circuit (hereinafter referred to as "DFF") which is formed by 2-INPUT AND 2-INPUT NOR gates (hereinafter abbreviated as, e.g., "2AND2NOR gate") 1.about.4 and an inverter 5 as shown in FIG. 1A is performed by supplying a reset signal S.sub.RST directly to a 2AND3NOR gate 13 at a master stage and a 2AND3NOR gate 12 at a slave stage as shown in FIG. 1B, so that the outputs of 2AND2NOR gates 11, 14 are set to "1" and the outputs of the 2AND3NOR gates 12, 13 are set to "0", respectively. To initialize a multi-register circuit such as a shift register, a plurality of DFFs each having a reset input are used so as to form the shift register and a reset input signal is directly applied to the respective DFFs.
FIG. 2A shows an example of a conventional shift register and FIG. 2B shows timing-charts thereof.
In the conventional shift register shown in FIG. 2A, a plurality of the D-type flip-flop circuits (DFFs) R0.about.R7, each having an internal circuit of the same circuit configuration as that shown in FIG. 1B, are connected in series and are commonly supplied with shift clocks S.sub.CK1, S.sub.CK2 and a reset signal S.sub.RST. A shift data D.sub.IN inputted from a shift data input terminal (D.sub.IN) is outputted from a shift data output terminal D.sub.OUT through the DFFs R0.about.R7. While the reset signal S.sub.RST remains "0" immediately after the power is turned on, the states of the DFFs R0.about.R7 are and remain undefined. When the reset signal S.sub.RST is set to "1", the outputs of the DFFs R0.about.R7 are all and immediately initialized to "0". Subsequently, the shift clocks S.sub.CK2 and S.sub.CK1 are supplied and, though not shown in the timing charts given in FIG. 2B, the shift data is inputted to the input terminal D.sub.IN of the shift register circuit and is shifted out from the output terminal D.sub.OUT.
One advantage of the above conventional shift register is that it can be immediately reset when the reset signal is set to "1" because each of the DFFs R0.about.R7 forming the shift register has a reset input terminal. However, since all bits are implemented by DFFs each having a reset input terminal, the shift register suffers from a disadvantage of requiring more logic elements in number than those which constitute DFFs having no reset input terminals as shown in FIG. 1A.
To avoid increasing in the number of elements, there has been known a shift register in which, as shown in FIG. 3A, a DFF having a reset input terminal is used for a DFF Q0 of the first stage and DFFs not having a reset input terminal are used for the remaining DFFs Q1.about.Q7 that follow. The operation of this shift register is described below. While the reset signal stays at "0" immediately after the power is turned on, the outputs of the DFFs Q0.about.Q7 remain undefined, respectively, as shown in the timing charts in FIG. 3B. When the reset signal S.sub.RST is set to "1", the first stage DFF Q0 is initialized immediately, but the remaining DFFs Q1.about.Q7 stay at undefined states since they are given no reset input.
Subsequently, when the shift clocks S.sub.CK1 and S.sub.CK2 are supplied to the respective DFFs with the reset signal being held at "1", the output "0" from the DFF Q0 is shifted into the following DFF Q1 in response to the first clock of the shift clocks, whereby the output of the DFF Q1 becomes "0". In response to the second clock of the shift clocks, the output of the DFF Q1 is shifted into the following DFF Q2 and, thus, the output of the DFF Q2 becomes "0". In a similar manner, the output of the DFF Q7 becomes "0" at last in response to the seventh clock of the shift clocks, thereby completing the initialization of the shift register. Thereafter, a shift data is loaded into the shift register from the data input terminal D.sub.IN.
Since the above circuit adopts only one DFF which is equipped with a reset input terminal, it contributes substantially to the reduction in the number of the necessary elements. However, as can be readily understood from the timing charts shown in FIG. 3B, the circuit takes an extra amount of time to generate the shift clocks that are necessary to completely initialize the entire shift register. This suffers from the disadvantages of increasing the initialization time and also making the shift clock control for the register initialization more complex.
As described above, the conventional register initialization circuits have problems in that the number of the necessary elements is increasing because of the need to directly supply the reset signal to the respective DFFs and, in that the initialization time has increased because of the need for generating shift clocks for initialization. These problems in the conventional shift registers are to be solved by the present invention.